when st4 => if (eoc =’0’)then next_state=st4;else next_state =st5; end if;

　　when st5 => next_state =st6;

　　when st6 => next_state =st0;

　　when others=> next_state =st0;

　　end case;

　　out4=current_state(5 downto 2);

　　ale=current_state(5); start =current_state(4);

　　oe=current_state(3); lock1=current_state(2);

　　end process;

　　process(clk)

　　begin

　　if (clk’event and clk =‘1’) then

　　current_state =next_state;

　　end if ;

　　end process ;

　　process (lock1)

　　if lock1=‘1’ and lock1’event then

　　regl=d ;

　　end if ;

　　end process ;

　　q=regl;

　　……