The clock & power management block consists of three parts:clock control, USB clk control, and power control.

Clock control logic

The Clock control logic in S3C2410X can generate the required clock signals includingFCLK for CPU, HCLK for
the AHB bus peripherals, and PCLK for the APB bus peripherals.

The S3C2410X has two Phase Locked Loops
(PLLs):one for FCLK, HCLK, and PCLK, and the other dedicated forUSB block (48Mhz).The clock control logic
can make slow clocks without PLL and connect/disconnect the clock to each peripheral block by software, which
will reduce the power consumption.

The main clock source comes from an external
crystal (XTIpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier),
which is connected to an external crystal, and also has two PLLs (Phase-Locked-Loop), which generate the high
frequency clock required in the S3C2410X.

MPLL鎖相環模塊（提供FLCK/HCLK（AHB）/PCLK(APB)） UPLL鎖相環模塊（提供UCLK）相同